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W971GG6JB
A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
BA2
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
0
0
PD
WR
DLL
TM
CAS Latency
BT
Burst Length
Mode Register
A8
0
1
DLL Reset
No
Yes
A7
0
1
Mode
Normal
Test
A3
0
1
Burst Type
Sequential
Interleave
Burst Length
A2 A1 A0
0 1 0
0 1 1
BL
4
8
BA1
BA0
MRS mode
0
0
MR
Write recovery for Auto-precharge
CAS Latency
0
1
1
1
0
1
EMR (1)
EMR (2)
EMR (3)
A11
0
0
A10
0
0
A9
0
1
WR *
Reserved
2
A6
0
0
A5
0
0
A4
0
1
Latency
Reserved
Reserved
0
1
0
3
0
1
0
Reserved
A12
0
1
Active power down exit time
Fast exit (use tXARD)
Slow exit (use tXARDS)
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
4
5
6
7
8
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
3
4
5
6
7
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL.
Figure 2 – Mode Register Set (MRS)
8.2.2
8.2.2.1
Extend Mode Register Set Commands (EMRS)
Extend Mode Register Set Command (1), EMR (1)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L, BA2 = "L" A0 to A12 =
Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (t MRD ) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used
for ODT setting.
Publication Release Date: Sep. 24, 2013
- 11 -
Revision A09
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